It is known that electrical noise occurs in large scale integration (LSI) semiconductor circuits due to alpha rays that occur when radioactive isotopes included in, for example, LSI packages or wiring decay, neutrons from cosmic rays, and the like, so that the semiconductor circuits malfunction. The aforementioned malfunction is called a soft error as opposed to a hard error due to a malfunction of hardware such as a semiconductor circuit. In dynamic random memories (DRAMs) and static random memories (SRAMs) memory elements of which have a small charge capacity, safeguards against soft errors have been considered from a long time ago. On the other hand, in logic LSIs, since the charge capacity of storage nodes of flip-flop circuits that are used as signal transmission circuits is large, safeguards against soft errors have been seldom considered.
However, as LSIs have been highly integrated and downsized, the charge capacity of storage nodes of flip-flop circuits that are used as signal transmission circuits has decreased. Moreover, LSI semiconductor circuits have come to handle signals having a small logical amplitude. Thus, in large scale integrations that are manufactured using the latest microfabrication technique, it has been found that the soft error rate that is an index of reliability is 1000 FIT (1000 FIT means that one error occurs in one million device (piece)×time (hour)) or more. The aforementioned soft error rate means that any one LSI malfunctions once in one month when 1000 LSIs are shipped.
Accordingly, proposals for improving the soft error tolerance of logic LSI circuits have been made. For example, the following proposal has been made for flip-flop circuits that are used in logic LSI circuits. A proposal (for example, Patent Document 1) has been made, in which the amount of charge collected in a node of a flip-flop circuit due to the incidence of alpha rays on a semiconductor substrate is first calculated, and the critical amount of charge necessary to invert the logic level of the node of the flip-flop circuit is calculated; then, the amount of capacity to be applied to the node of the flip-flop circuit to prevent soft errors when the amount of the collected charge is larger than the critical amount of charge is calculated; and then, the amount of capacity to be applied is applied to the node of the flip-flop circuit.
(Refer to Japanese Laid-open Patent Publication No. 2000-195274)
Adding a capacitance to flip-flop circuits used in signal transmission circuits uniformly to prevent inversion of the logic level in the flip-flop circuits results in a delay in signal transmission in all the signal transmission circuits and thus may result in the whole of a logic LSI circuit being unable to follow a high-speed operation. For example, operation with a clock signal having a predetermined clock frequency may not be guaranteed.
On the other hand, in view of the operation of a signal transmission circuit, it is apparent that, when inversion of the logic level does not occur in a flip-flop circuit, no soft error is recognized. However, even in a case where inversion of the logic level occurs, when it does not happen that a signal the logic level of which is inverted is transferred from a flip-flop circuit in which inversion of the logic level occurs to the next flip-flop circuit and latched, no soft error is recognized. Thus, methods other than the method for adding a capacitance to flip-flop circuits used in signal transmission circuits uniformly may be considered as methods for improving the soft error tolerance.
Moreover, even when a signal the logic level of which is inverted is latched into the next flip-flop circuit, a method for preventing soft errors by performing error checking by taking the parity among the logics of a plurality of signals and retrying instructions exists. However, in the aforementioned method, the performance of a logic LSI circuit is significantly decreased.